Multiple-valued Logic Research Articles

Note on Partial Falsifiability of Fuzzy and Fuzzy-Extension Hypotheses

In this short note, we adjust the (classical) Falsifiability of a hypothesis that may be 100% true as in classical logic, to the field of multi-valued logics, where there are partialities of truth-value, of indeterminacy, and of false-value of a hypothesis, and we call it Partial Falsifiability.

Ternary logic in the optical controlled-SWAP gate based on Laguerre-Gaussian modes of light

The need set by a computational industry to increase processing power, while simultaneously reducing the energy consumption of data centers, became a challenge for modern computational systems. In this work, we propose an optical communication solution, that could serve as a building block for future computing systems, due to its versatility. The solution arises from Landauer’s principle and utilizes reversible logic, manifested as an optical logical gate with structured light, here represented as Laguerre-Gaussian modes. We introduced a phase-shift-based encoding technique and incorporated multi-valued logic in the form of a ternary numeral system to determine the similarity between two images through the free space communication protocol.

A Mixture of Negative-, Zero-, and Positive-Differential Transconductance Switching from Tellurium/Indium Gallium Zinc Oxide Heterostructures.

Conventional transistors have long emphasized signal modulation and amplification, often sidelining polarity considerations. However, the recent emergence of negative differential transconductance, characterized by a drain current decline during gate voltage sweeping, has illuminated an unconventional path in transistor technology. This phenomenon promises to simplify the implementation of ternary logic circuits and enhance energy efficiency, especially in multivalued logic applications. Our research has culminated in the development of a sophisticated mixed transconductance transistor (M-T device) founded on a precise Te and IGZO heterojunction. The M-T device exhibits a sequence of intriguing phenomena, zero differential transconductance (ZDT), positive differential transconductance (PDT), and negative differential transconductance (NDT) contingent on applied gate voltage. We clarify its operation using a three-segment equivalent circuit model and validate its viability with IGZO TFT, Te TFT, and Te/IGZO TFT components. In a concluding demonstration, the M-T device interconnected with Te TFT achieves a ternary inverter with an intermediate logic state. Remarkably, this configuration seamlessly transitions into a binary inverter when it is exposed to light.

A ternary gate-connected threshold switching thin-film transistor

Multi-valued logic has been a significant focus of research in various fields with the advancement of information technology. One approach to realizing ternary logic is integrating of a threshold switching (TS) device with a transistor, but this method often entails a complex fabrication process. This work suggests a ternary gate-connected threshold switching thin-film transistor (TS-TFT) by serially connecting the TS device with a bottom-gate thin-film transistor (TFT). The fabrication process is simplified with a structure that shares electrodes and insulators. Different threshold voltages from TS and TFT devices produce stable multiple states. The Pt/HfO2/TiN TS device has an electronic trapping/detrapping switching mechanism that exhibits low power consumption and high reliability. With the superior electrical performance of an amorphous indium gallium zinc oxide TFT, the TS-TFT has stable endurance. Furthermore, pulse switching and ternary inverter are demonstrated from the practical point of view.

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Multiple Value Logic (MVL) circuits in high-speed digital systems can represent significantly more information than traditional binary logic circuits. The increasing demand for enhanced data storage capacity has driven the adoption of MVL circuits. However, designing MVL circuits presents challenges, particularly in achieving improved performance aligned with the desired threshold voltage. To address this challenge, harnessing carbon nanotube field-effect transistors (CNTFETs) has been instrumental in designing MVL circuits. CNTFETs offer distinct advantages due to their large resistors. Furthermore, substituting these resistors with Resistive Random Access Memory (RRAM) to implement Ternary logic circuits enhances storage capacity by enabling multiple resistance states within a single cell. This paper presents a novel MVL circuit design that leverages the unique characteristics of CNTFETs and RRAM. Additionally, gate implementation is explored using a Recurrent Neural Network − Long-Short Term Memory (RNN-LSTM) based Tasmanian Devil Optimization algorithm. The practical implementation uses Synopsis HSPICE software with CNTFET technology at 32 nm. A comprehensive performance analysis compares this approach with state-of-the-art solutions regarding delay, area, and power consumption. Significant reductions in area, power consumption, and transistor count are revealed with the proposed approach.

Implementation of Full adder in Multiple valued Logic for Performance Optimization

Multiple valued logic is now becoming more significant in real-world applications. Mathematical design blocks are essential in digital and mixed-signal systems. A system's arithmetic blocks often use the most power because of the high switching activity. Implementations of quaternary arithmetic may be a way to cut down on energy use while improving system performance. In this paper, quaternary adders are developed using three different approaches, and their binary equivalents are evaluated in terms of size, predicted logic depth, and performance estimation.

Tri-state GNRFET-based fast and energy-efficient ternary multiplier

As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.

IBA-VNS: A Logic-Based Machine Learning Algorithm and Its Application in Surgery

The interpretability and explainability of machine learning (ML) approaches play a key role in the trustworthiness of ML models in various applications. The objective of this paper is to incorporate a logic-based reasoning in the ML model that is not only accurate but also interpretable and easily applied. More precisely, we propose a hybrid IBA-VNS approach based on interpolative Boolean algebra (IBA) and variable neighborhood search (VNS). IBA is chosen over traditional multi-valued and/or fuzzy logic techniques due to its consistency in preserving all Boolean axioms. The VNS heuristic is used for model training, i.e., determining the optimal logical aggregation function within the IBA framework for solving observed prediction problems. Obtained logic aggregation functions are easy to understand and may provide additional insight to the decision-maker. The proposed approach does not require any domain knowledge and is applicable in various domains. IBA-VNS is evaluated on several standard datasets. Further, IBA-VNS is applied to the real-world problem of predicting hospital length of stay (LOS), showing exceptional results in terms of interpretability and accuracy. In fact, the dataset is collected from the LabSerb program regarding colorectal surgeries in the period 2015–2023. The proposed approach extracted knowledge regarding the problem, i.e., the causal relations between the patient’s health condition and LOS, along with achieving an MAE of 1.144 days.

Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing.

Negative-differential-resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal-insulator-semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static-random-access-memory, which are essential components in the development of multivalued logic computing technology.

Remora Optimized Dynamic Neural Network to Design Low-Power CNTFET Logic Gate Realization with Multiple-Valued Circuits

The emerging trend of new digital technology leads to the requirement of small, faster, and low-power consumed processors. The advanced 5 G technology forces the usage of enhanced battery life, maximized spectral efficiency, etc., these can be achieved by the inclusion of a Carbon nanotube field-effect transistor (CNTFET). The proposed multiple-valued logic circuits (MVL) are designed using some of the unique features of the CNTFET such as high transconductance, setting of desired threshold voltage, and similar mobility of P and N-type devices. For designing low-power and optimized logic gate realization we have utilized the inherent binary gates along with the CMOS architecture. Further, an artificial intelligence approach known as Dynamic Neural Network (DNN) is adopted for the realization of logic gates in the MVL with the employment of lesser MVL operators. To enhance the parameter utilization of DNN with the help of tuning, we exploited the Remora Optimization algorithm (ROA). The results are obtained by conducting experiments on HFSS software. This approach is designed to reduce the static power dissipation, the number of logic gates, and network propagation delay. Compared to the existing methods, the proposed technique outlined a standard voltage of 32 nm that considers 0.9 V supply voltage. The result of our proposed method can be deviated by only 25% and thus outperforms all the other approaches. The standby power consumption of proposed approach is 2.12 W

Charge transfer mechanism for realization of double negative differential transconductance

With development of information age, multi-valued logic (MVL) technology utilizing negative differential transconductance (NDT) phenomenon has drawn attention as next-generation computing technology that can replace binary logic. However, because conventional NDT devices primarily use ternary logic, multiple-peak NDT device is required for higher-radix MVL that can process more datasets. Here, van der Waals double-peak anti-ambipolar transistor (AAT) as NDT device was developed by utilizing peak voltage (Vpeak) modulation of NDT peak. For realization of quaternary logic, Vpeak modulation technology was developed through charge transfer mechanism from channel, thereby shifting NDT peak and increasing peak-to-valley current ratio (PVCR). Furthermore, Double-peak AAT was implemented through parallel configuration of two AATs with different Vpeak values. Finally, quaternary inverter with four widely stable logic states was implemented by utilizing the developed double-peak AAT with two distinct NDT peaks and high PVCR. This double-peak AAT is expected to contribute to the development of next-generation MVL technology capable of processing datasets.

A review on multiple-valued logic circuits

Since the traditional binary logic has several disadvantages including inaccuracy, high complexity, and limited applications. Multiple-Valued Logic (MVL), which can store more information in one digit than binary logics, require less number of logic gates and take the third value in practical logic problems, is developed and introduced. More information stored per digit leads to higher computational efficiency. Less logic gates results in more spaces on the circuit board. Considering the third value means higher accuracy. In this research, some examples of different MVL circuit are designed to give a rough picture of current research in this domain. These designs are based on ternary and quaternary logics rather than binary logics. Besides, reliability evaluation through mathematical approach is presented in order to prove that the new design is more preferable. This can be carried out with mathematical analysis such as calculating a matrix that reflects its reliability, and simulating different designs to obtain certain values and comparing them with each other. Despite facing various challenges, including complicated physical implementation and difficulty to modulate the signals. This means that there is still potential of further research in this domain of logic circuits. This result in the conclusion that the MVL logic circuits will replace the conventional binary logic circuits in the future, and probably that decimal logic would be developed and no binary-to-decimal conversion unit will be required.

Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture

The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high ON/OFF current ratio of 109 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits significant data retention attributes during memory operations for up to 103 s. The SiNT FBFET-based inverter circuit retains output logic states of “1” and “0” for 1.705 s and 1.948 s, respectively, at megahertz operating frequency without standby power consumption. Additionally, SiNT FBFET has also been used to build ternary NAND/NOR logic gates with memory functionality. Numerical mixed-mode simulations of the circuits have been carried out using the commercially available Synopsys “Sentaurus” TCAD tool for examining the performance and memory characteristics of SiNT FBFETs. This study demonstrates the possible use of SiNT FBFET in multivalued logic systems and the development of next-generation memory devices.

An energy-efficient design of ternary SRAM using GNRFETs

ABSTRACT The primary requirement of internet-of-things (IoT) applications is to have an energy-efficient design that extends the battery life for long-term operation. To achieve energy efficiency, one can employ multiple-valued logic (MVL) instead of binary logic and utilise graphene nanoribbon field-effect transistors (GNRFETs) as variable-threshold voltage (V th ) capable devices. The implementation of an MVL system enhances data transferability and reduces the number of interconnections, resulting in improved energy consumption compared to a binary system. In such systems, static random access memory (SRAM), which serves as a crucial component of very large-scale integrated (VLSI) chips, dominates energy consumption. This research paper introduces an energy-efficient ternary SRAM using GNRFETs. We propose a standard ternary inverter based on GNRFET devices, which serves as the fundamental building block of a storage cell. Simulation results conducted on a 32-nm GNRFET with a 0.9 V supply voltage demonstrate that the proposed design achieves energy consumption improvements ranging from 46.39% to 98.16% compared to the most recent ternary SRAMs. Furthermore, the SRAM cell is evaluated under various processes and environmental parameter variations.

Model-based project management using artificial intelligence tools

Subject. The article addresses project management issues. Objectives. The aim is to reveal the main directions of development of the theory and practice of model-based project management, using artificial intelligence tools. Methods. The study rests on the methodology of systems analysis and process-oriented approach, employs methods of modeling and comparative analysis. Results. We define the current technology of decision-making to minimize risk, describe ideas of creating a decision support system with elements of artificial intelligence, present an experiment on implementing a model of operational monitoring of risk objects at the stage of documentary customs control. The paper identifies expedient priority organizational solutions in the customs risk management system, provides proposals on the structure of the customs risk service, describes the concept of hybrid intelligence, implemented on the basis of a neural network, to be integrated in the process of collective decision-making. We present artificial intelligence technologies used in the practice of project management, disclose their advantages and disadvantages. Conclusions. The decision-making process is described as a process of structuring the vision of strategic perspective by the head and/or experts, the formation and adaptation of knowledge to real conditions of customs construction, or as a process of project management. The paper introduces the concept and reveals the technology of collective work of experts (technology of expert-analytical modeling) during the formulation of problems and preparation of managerial, methodological, technological, and other solutions. Within the technology, a multi-valued logic of phased transformation of experts' vision into a new system of customs organization, with a step-by-step assessment of generated situational alternatives is built on the formed set of conditions.

Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic Circuits.

Multivalued logic (MVL) technology is a promising solution for improving data density and reducing power consumption in comparison to complementary metal-oxide-semiconductor (CMOS) technology. Currently, heterojunction transistors (TRs) with negative differential transconductance (NDT) characteristics, which play an important role in the function of MVL circuits, adopt organic or 2D semiconductors as active layers, but it is still difficult to apply conventional CMOS processes. Herein, we demonstrate an oxide semiconductor (OS) heterojunction TR with NDT characteristics composed of p-type copper(I) oxide (Cu2O) and n-type indium gallium zinc oxide (IGZO) using the conventional CMOS manufacturing processes. The electrical characteristics of the fabricated device exhibit a high Ion/Ioff ratio (∼3 × 103), wide NDT ranges (∼29 V), and high peak-to-valley current ratios (PVCR ≈ 25). The electrical properties of 15 devices were measured, confirming uniform performance in the PVCR, NDT range, and Ion/Ioff ratio. We analyze the device operation by varying the source/drain (S/D) position and changing the device geometry and the thickness of the Cu2O layer. Additionally, we demonstrate heterojunction ambipolar TR to elucidate the transport mechanism of NDT devices at a high gate voltage (VGS). To confirm the feasibility of the MVL circuit, we present a ternary inverter with three clearly expressed logic states that have a long intermediate state and greater margin of error induced by wide NDT regions and high PVCR.

Dynamic Many-Valued Logic Systems in Theoretical Economics

Dynamic Many-Valued Logic Systems in Theoretical Economics

Finiteness of One-Valued Function Classes in Many-Valued Logic

This paper addresses the theoretical issues in k-valued logic, which are crucial for developing solutions in various fields of science and technology. One of the fundamental issues is a complete description of the closed classes of functions of three-valued logic. The explicit description of closed classes in multivalued logic is an open problem. In this study, we consider a special case of the finite generation of all closed classes of three-valued logic through the operation of superposition. Previously, we considered the issue of the finite generation of classes containing a subset of single-variable functions. We have also provided a description of superlattices (lattices of lattices) containing a precomplete class of unary functions. The finite generation of these superlattices is proved. On the basis of these results, in this paper, we have proven that any class containing any of the precomplete classes from the set of single-valued functions is also finitely generated. The main result of this paper consists of three theorems on the finite generation of classes containing precomplete classes of single-valued functions and classes including all monotone unary functions. Thus, the obtained theoretical result provides easily verifiable criteria for the finiteness of classes of multivalued logic functions. It allows you to use simple procedures instead of cumbersome explicit constructs. The finite generation of overlattices allows the development of digital computing circuits that are crucial for practical applications. The proofs are based on an explicit description of these classes by an induction in the number of variables and essentially use the properties of functionally closed (Burle) classes of functions.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

INDICATORS OF INFORMATION FEATURES FOR RECOGNISING THE STATE OF SOURCES AND OBJECTS OF TELECOMMUNICATION NETWORKS AND SYSTEMS

Background. The majority of modern procedures for the recognition of radio sources and objects are based on the use of binary and multivalued logic, which have low specific features. The essence of the issues is to compare a priori knowledge and a posteriori data coming from the surveillance means and to make a decision on the recognition of a radio emission object. A priori knowledge and a posteriori data are formed both before and during the recognition process on the basis of sets of information features or information signatures. At the same time, when constructing an integral indicator for determining the affiliation and status of sources and objects, it is necessary to know the weighting coefficients of information features, the determination of which is a rather difficult task. Therefore, the issue of determining the weighting coefficients that characterise information features remains an urgent task in the field of statistical radio engineering.
 Objective. The purpose of the paper is to select and substantiate a simple and effective method for calculating the weighting coefficients of information features for the implementation of the methodology for recognising radio sources and objects.
 Methods. Decision-making on the value of the weighting coefficients of information features of the recognition objects belonging to a certain class is based on the results of calculations using one of the three Fishburne formulae, which, in comparison with the known methods of expert assessments, are very simple and understandable, do not require any additional research and complex calculations.
 Results. The procedure is proposed and an example of using the Fishburne method (three formulae) in calculating the value of the weighting coefficients of information features for recognising sources and objects of radio monitoring is considered.
 Conclusions. Comparison of the method of calculating the weighting coefficients using Fishburne's formulae with other known methods of expert assessments shows that there is no need to interview experts and process their analysis results; there are no restrictive implementation conditions; it is easy to take into account additional information about the indicators, if necessary; no software implementation with a complex search algorithm is required; it is easy to make any changes as additional information indicators.